This invention relates to differential amplifiers and, more particularly, to f.sub.T doubler amplifiers of the type having a common base stage.
FIGS. 1A through 1C show the evolution of the prior art prior to one embodiment of the present invention. In FIG. 1A, a differential amplifier and common base stage is shown. The amplifier includes transistors 6 and 8 whose emitters are coupled through resistor 5, which has a value of R ohms. The bases of transistors 6 and 8 are respectively coupled to the input terminals 18 and 20 through input resistors 22 and 24. A differential input voltage V.sub.I is coupled between input terminals 18 and 20. Bias current for transistors 6 and 8 is provided by constant current sources 7 and 9, each having a value of 2I milliamps. The common base stage for the amplifier includes transistors 2 and 4, the bases of transistors 2 and 4 being coupled to a source of reference voltage, V.sub.R. The differential output current provided by transistors 2 and 4 is converted to a differential output voltage at output terminals 14 and 16 by load resistors 10 and 12 that are coupled to a source of positive voltage, V.sub.CC.
The amplifier in FIG. 1B, designated as a Darlington type f.sub.T doubler amplifier, has an improved frequency response beyond the amplifier shown in FIG. 1A. Transistors 6 and 8 have been each replaced by two transistors arranged in a Darlington configuration. Transistor 6 has been replaced by transistors 63 and 61 and transistor 8 has been replaced by transistors 83 and 81. Emitter resistor 5 has been replaced by emitter resistors 51 and 53. Resistor 51 has a value of 2R ohms and couples the emitters of transistors 61 and 81. Resistor 53 also has a value of 2R ohms and couples the emitters of transistors 63 and 83, as well as being coupled between the bases of transistors 61 and 81. The bias for transistors 63, 61, 81, and 83 is provided by current sources 73, 71, 91, and 93, respectively. Each current source has a value of 1 milliamps. The remainder of the amplifier in FIG. 1B is identical to the amplifier shown in FIG. 1A.
Since each of the transistors 63, 61, 81, and 83 operate at half the current of transistors 6 and 8 of the amplifier shown in FIG. 1A and because resistors 51 and 53 are twice the value of resistor 5, the input capacitance is lowered by approximately a factor of two. However, the total gain of the amplifier is the same as the amplifier of FIG. 1A. (One half the gain attributed to transistors 63 and 83, and one half the gain attributed to transistors 61 and 81). Assuming that the bandwidth of the amplifier is limited by the input circuit, the reduction of the input capacitance by a factor of two coupled with the same overall amplifier gain results in an improvement in frequency response by approximately a factor of two. Additionally, the input bias current seen at input terminals 18 and 20 is reduced by a factor of two as well as the variation in input bias current with transistor beta.
The amplifier in FIG. 1C is also a Darlington type f.sub.T doubler amplifier and has an improved common base stage over the amplifier shown in FIGS. 1A-B. Transistors 2 and 4 have been each replaced by two transistors arranged in a Darlington configuration. Transistor 2 has been replaced by transistors 23 and 21 and transistor 4 has been replaced by transistors 43 and 41. The addition of the Darlington common base stage significantly reduces base current losses through transistors 2 and 4. The remainder of the amplifier shown in FIG. 1C is identical to the amplifier shown in FIG. 1B.
FIGS. 3A through 3C show the evolution of the prior art up to another embodiment of the present invention. FIG. 3A is identical to FIG. 1A and is reproduced to help illustrate the evolution of the other embodiment.
The amplifier in FIG. 3B, designated as a series input-parallel output type f.sub.T doubler amplifier, has an improved frequency response beyond the amplifier shown in FIG. 3A. The circuit in FIG. 3B was invented by Carl Battjes and is explained in detail in U.S. Pat. No. 3,633,120 entitled "Amplifier Circuit" that is herein incorporated by reference. Transistors 6 and 8 have been each replaced by two differential pairs coupled to V.sub.R2, a source of reference voltage. Transistor 6 has been replaced by transistors 66 and 68 and transistor 8 has been replaced by transistors 86 and 88. Emitter resistor 5 has been replaced by emitter resistors 56 and 58. Resistor 56 has a value of 2R ohms and couples the emitters of transistors 68 and 86. Resistor 58 also has a value of 2R ohms and couples the emitters of transistors 66 and 88. The bias for transistors 68, 86, 66, and 88 is provided by current sources 78, 96, 76, and 98, respectively. Each current source has a value of 1 milliamps. The remainder of the amplifier in FIG. 3B is identical to the amplifier shown in FIG. 3A.
The analysis of the frequency response of the f.sub.T doubler shown in FIG. 3B is identical to that of the f.sub.T doubler shown in FIG. 1B. Each of the transistors 68, 86, 66, and 88 operate at half the current and are emitter coupled to twice the emitter resistance of transistors 6 and 8 of the amplifier shown in FIG. 3A. Therefore the input capacitance is lowered by approximately a factor of two. The total gain of the amplifier is the same as the amplifier of FIG. 3A. (One half the gain attributed to transistors 68 and 86, and one half the gain attributed to transistors 66 and 88). Assuming the bandwidth is limited by the input circuit, the reduction of the input capacitance by a factor of two coupled with the same overall amplifier gain results in an improvement in frequency response by approximately a factor of two. Additionally, the input bias current seen at input terminals 18 and 20 is reduced by a factor of two as well the variation in input bias current with transistor beta.
The amplifier in FIG. 3C is also a series input-parallel output type f.sub.T doubler amplifier and has an improved common base stage over the amplifier shown in FIGS. 3A-B. Transistors 2 and 4 have been each replaced by two transistors arranged in a Darlington configuration. Transistor 2 has been replaced by transistors 28 and 26 and transistor 4 has been replaced by transistors 48 and 46. The addition of the Darlington common base stage significantly reduces base current losses through transistors 2 and 4. The remainder of the amplifier shown in FIG. 3C is identical to the amplifier shown in FIG. 3B.
The amplifiers shown in FIGS. 1B-C and FIGS. 3B-C may also be designated as distributed amplifiers in that the total gain is distributed between two amplifier stages. In such amplifiers it is important that individual contributions from each amplifier stage sum in phase and without delay between stages. The Darlington common base stage in FIGS. 1C and 3C do not correctly sum the individual contributions from each amplifier stage. Briefly stated, the problem lies in the distributed nature of the amplifier stages as well as in the Darlington common base stage. Using the amplifier in FIG. 1C as an example, the signal contributions from the stage coupled to the voltage input signal, transistors 63 and 83, are passed through a relatively low delay path (relatively lower delay is referred to subsequently as "fast"), which includes transistors 23 and 43. The signal contributions from the stage including transistors 61 and 81 is delayed due to the finite delay provided by transistors 63 and 83. However, this delayed signal is further delayed by a relatively higher delay path (relatively higher delay is referred to subsequently as "slow"), which includes transistors 21 and 41. The result is that the signal contributions are significantly delayed, one from the other. Therefore, in response to an input voltage pulse, an output voltage pulse is produced at output terminals 10 and 12 that has undesirable transient response due to phase distortion such as overshoot, undershoot, or a combination thereof.
What is desired is an f.sub.T doubler amplifier having a Darlington type common base stage that adjusts the phase of signal contributions at the output to produce an improvement in bandwidth and transient response.